[ExaGraph] Graphs and HPC: Lessons for Future Architecture

Graphs and HPC: Lessons for Future Architectures, Bruce Hendrickson (Sandia)

http://science.energy.gov/~/media/ascr/ascac/pdf/meetings/oct08/hendrickson_ascac.pdf

Cray のアーキテクチャに偏ったスライド. BlueGene/L との比較も少しあり。

グラフ解析問題の特徴
Runtime is dominated by latency
Potentially random accesses to global address space
Perhaps many at once, but parallelism is fine-grained
Essentially no computation to hide memory costs
Access pattern is data dependent
Prefetching unlikely to help
Usually only want small part of cache line –
levels of memory all Potentially abysmal locality at hierarchy

以上のグラフ解析の要件を満たすアーキテクチャ
Low latency / high bandwidth for small messages!
Latency tolerant
Light-weight synchronization mechanisms
Global address space
- Obviate the need for partitioning –
- Avoid memory-consuming profusion of ghost-nodes –
- No local/global numbering conversions –
- Support fine-grained parallelism –
- One machine with these properties is the Cray MTA-2, XMT