ラベル graph500 の投稿を表示しています。 すべての投稿を表示
ラベル graph500 の投稿を表示しています。 すべての投稿を表示

2011年12月13日火曜日

An In-Depth Study of Stochastic Kronecker Graphs

ICDM に参加中の村田先生からのメッセージ。

"An In-Depth Study of Stochastic Kronecker Graphs"
C. Seshadhri, Ali Pinar, and Tamara G. Kolda,
Proceedings of the 11th IEEE International Conference on
Data Mining, pp.587-596, 2011.
http://arxiv.org/abs/1102.5046

タイトルの通り、(Graph500で用いられる)Kronecker Graphの研究です。発表を聞いただけで論文はまだ読んでいないのですが、
・次数分布はheavy tailでもpower lawでもなく、論文中の図の
ように何度もバウンドしたような曲線になる
・ノイズを入れたnoisy SKGになると次数分布が直線に近づく
・孤立点が多い。k=42で74%が孤立点
・coreのサイズは実ネットワークのそれより小さい

2011年12月1日木曜日

Graph500 on Amazon EC2 (Cluster Computer Instances)

http://aws.amazon.com/jp/hpc-applications/

23 GB メモリ
33.5 EC2 Compute Unit(2 x Intel Xeon X5570、quad-core「Nehalem」アーキテクチャ)
1690 GB インスタンスストレージ
64ビット プラットフォーム
I/O 性能: 超高速(10 ギガビットイーサネット)
API 名: cc1.4xlarge

Cluster Compute Eight Extra Large を使用すると、1時間 2.40 $.
128 ノードを1時間使用すると、1ドル80円計算で 約 25000円.

Madduri's work

http://www.cc.gatech.edu/~bader/papers/ShortestPaths.html

Parallel Shortest Path Algorithms for Solving Large-Scale Instances

We present an experimental study of the single source shortest path problem with non-negative edge weights (NSSP) on largescale graphs using the Delta-stepping parallel algorithm. We report performance results on the Cray MTA-2, a multithreaded parallel computer. The MTA-2 is a high-end shared memory system offering two unique features that aid the efficient parallel implementation of irregular algorithms: the ability to exploit fine-grained parallelism, and low-overhead synchronization primitives. Our implementation exhibits remarkable parallel speedup when compared with competitive sequential algorithms, for low-diameter sparse graphs. For instance, Delta-stepping on a directed scale-free graph of 100 million vertices and 1 billion edges takes less than ten seconds on 40 processors of the MTA-2, with a relative speedup of close to 30. To our knowledge, these are the first performance results of a shortest path problem on realistic graph instances in the order of billions of vertices and edges.

HPC Graph Analytics

http://www.graphanalysis.org/benchmark/GraphAnalysisBenchmark-v1.0.pdf

Distributed Graph Analytics

http://dl.acm.org/citation.cfm?id=958940
Δ-stepping: a parallelizable shortest path algorithm

The single source shortest path problem for arbitrary directed graphs with n nodes, m edges and nonnegative edge weights can sequentially be solved using O(n ċ log n + m) operations. However, no work-efficient parallel algorithm is known that runs in sublinear time for arbitrary graphs. In this paper we present a rather simple algorithm for the single source shortest path problem. Our new algorithm, which we call Delta-stepping, can be implemented very efficiently in sequential and parallel setting for a large class of graphs. For random edge weights and arbitrary graphs with maximum node degree d, sequential Δ-stepping needs O(n + m + d ċ L) total average-case time, where L denotes the maximum shortest path weight from the source node s to any node reachable from s. For example, this means linear time on directed graphs with constant maximum degree. Our best parallel version for a PRAM takes O(d ċ L ċ log n + log2 n) time and O(n + m + d ċ L ċ log n) work on average. For random graphs, even O(log2 n) time and O(n + m) work on average can be achieved. We also discuss how the algorithm can be adapted to work with nonrandom edge weights and how it can be implemented on distributed memory machines. Experiments indicate that already a simple implementation of the algorithm achieves significant speedup on real machines.


Single-Source Shortest Paths with the Parallel Boost Graph Library
http://www.dis.uniroma1.it/~challenge9/papers/edmonds.pdf
The Parallel Boost Graph Library (Parallel BGL) is a library of graph algorithms and data structures for distributed-memory computation on large graphs. Developed with the Generic Programming
paradigm, the Parallel BGL is highly customizable, supporting various graph data structures, arbitrary
vertex and edge properties, and different communication media. In this paper, we describe the implementation of two parallel variants of Dijkstra’s single-source shortest paths algorithm in the Parallel BGL.We also provide an experimental evaluation of these implementations using synthetic and real-world benchmark graphs from the 9th DIMACS Implementation Challenge.


http://eecs.wsu.edu/~cs460/cs550/parallelShortestPath.pdf
A Parallel Shortest Path Algorithm Based on Graph-Partitioning and Iterative Correcting, 2010
In this paper, we focus on satisfying the actual demands of quickly finding the shortest paths over real-road networks in an intelligent transportation system. A parallel shortest path algorithm based on graph partitioning and iterative correcting is proposed. After evaluating the algorithm using three real road networks, we conclude that our graph- partitioning and iterative correcting based parallel algorithm has good performance. In addition, it achieves more than a 15-fold speedup on 16 processors in an IBM cluster over these real road networks.


http://scidok.sulb.uni-saarland.de/volltexte/2004/207/pdf/UlrichMeyer_ProfDrKurtMehlhorn.pdf
Design and Analysis of Sequential and Parallel Single–Source Shortest–Paths Algorithms, Ulrich Meyer

e study the performance of algorithms for the Single-Source Shortest-Paths (SSSP) problem on graphs with nodes and edges with nonnegative random weights. All previously known SSSP algorithms for directed graphs required superlinear time. We give the first SSSP algorithms that provably achieve linear average-case execution time on arbitrary directed graphs with random edge weights. For independent edge weights, the linear-time bound holds with high probability, too. Additionally, our result implies im- proved average-case bounds for the All-Pairs Shortest-Paths (APSP) problem on sparse graphs, and it yields the first theoretical average-case analysis for the “Approximate Bucket Implementation” of Dijkstra’s SSSP algorithm (ABI–Dijkstra). Furthermore, we give con- structive proofs for the existence of graph classes with random edge weights on which ABI–Dijkstra and several other well-known SSSP algorithms require superlinear average- case time. Besides the classical sequential (single processor) model of computation we also consider parallel computing: we give the currently fastest average-case linear-work parallel SSSP algorithms for large graph classes with random edge weights, e.g., sparse random graphs and graphs modeling the WWW, telephone calls or social networks.


http://www.cse.psu.edu/~madduri/papers/ThorupSSSP-MTAAP07.pdf


http://www.sandia.gov/~sjplimp/papers/pc11.pdf
MapReduce in MPI for Large-scale Graph Algorithms, 2010

We describe a parallel library written with message-passing (MPI) calls that allows algo- rithms to be expressed in the MapReduce paradigm. This means the calling program does not need to include explicit parallel code, but instead provides “map” and “reduce” functions that operate independently on elements of a data set distributed across processors. The library performs needed data movement between processors. We describe how typical MapReduce functionality can be implemented in an MPI context, and also in an out-of-core manner for data sets that do not fit within the aggregate memory of a parallel machine. Our motivation for creating this library was to enable graph algorithms to be written as MapReduce opera- tions, allowing processing of terabyte-scale data sets on traditional MPI-based clusters. We outline MapReduce versions of several such algorithms: vertex ranking via PageRank, triangle finding, connected component identification, Luby’s algorithm for maximally independent sets, and single-source shortest-path calculation. To test the algorithms on arbitrarily large artifi- cial graphs we generate randomized R-MAT matrices in parallel; a MapReduce version of this operation is also described. Performance and scalability results for the various algorithms are presented for varying size graphs on a distributed-memory cluster. For some cases, we com- pare the results with non-MapReduce algorithms, different machines, and different MapReduce software, namely Hadoop. Our open-source library is written in C++, is callable from C++, C, Fortran, or scripting languages such as Python, and can run on any parallel platform that supports MPI.


Apache HAMA http://blogs.apache.org/hama/


http://homepages.dcc.ufmg.br/~tmacam/publications/macambira2010middleware.pdf
A middleware for parallel processing of large graphs, 2010
With the increasing “data deluge” scientists face today, the analysis and processing of large datasets of structured data is a daring task. Among such data, large graphs are gaining particular importance with the growing interest on social networks and other complex networks. Given the dimensions considered, parallel pro- cessing is essential. However, users are generally not experts in writing parallel code to handle such structures. In this work we present Rendero, a middleware that makes it possible to easily de- scribe graph algorithms in a form adequate for parallel execution. The system is based on the Bulk-Synchronous programming model and offers a vertex-based abstraction. Our current implementation offers good speed-up and scale-up results for large graphs ranging from tens of thousands to millions of vertices and edges in some cases.


http://www.cslab.ntua.gr/~anastop/files/papers/mtaap09dijkstra.pdf
Early Experiences on Accelerating Dijkstra’s Algorithm Using Transactional Memory

In this paper we use Dijkstra’s algorithm as a challenging, hard to parallelize paradigm to test the efficacy of several par- allelization techniques in a multicore architecture. We consider the application of Transactional Memory (TM) as a means of concurrent accesses to shared data and compare its perfor- mance with straightforward parallel versions of the algorithm based on traditional synchronization primitives. To increase the granularity of parallelism and avoid excessive synchro- nization, we combine TM with Helper Threading (HT). Our simulation results demonstrate that the straightforward par- allelization of Dijkstra’s algorithm with traditional locks and barriers has, as expected, disappointing performance. On the other hand, TM by itself is able to provide some performance improvement in several cases, while the version based on TM and HT exhibits a significant performance improvement that can reach up to a speedup of 1.46.

GPU-based SSSP

http://www.ijcaonline.org/volume10/number10/pxc3871992.pdf
Performance Improvement in Large Graph Algorithms on GPU using CUDA: An Overview, 2010

The basic operations on the graphs with millions of vertices are common in various applications. To have faster execution of such operations is very essential to reduce overall computation time. Today’s Graphics processing units (GPUs) have high computation power and low price. This device can be treated as an array of Single Instruction Multiple Data (SIMD) processors using CUDA software interface by Nvidia. Massively Multithreaded architecture of a CUDA device makes various threads to run in parallel and hence making optimum use of available computation power of GPU. In case of graph algorithms, vertices of the graphs are processed in parallel by mapping them to various threads on device. By making thousands of threads to run in parallel, computation time required for these algorithms is drastically decreased as compared to their CPU implementation.
We studied different parallel algorithms for Breadth first search, all pairs shortest path that are carried out on GPU using CUDA and make their comparative study with respect to execution time, data structure used, input data etc. In the paper, we presented overview of various parallel methods carried out on GPU using its multithreaded architecture for BFS, APSP by various authors.


http://ppl.stanford.edu/papers/ppopp070a-hong.pdf
Accelerating CUDA Graph Algorithms at Maximum Warp, 2007
Graphs are powerful data representations favored in many compu- tational domains. Modern GPUs have recently shown promising re- sults in accelerating computationally challenging graph problems but their performance suffers heavily when the graph structure is highly irregular, as most real-world graphs tend to be. In this study, we first observe that the poor performance is caused by work imbal- ance and is an artifact of a discrepancy between the GPU program- ming model and the underlying GPU architecture. We then propose a novel virtual warp-centric programming method that exposes the traits of underlying GPU architectures to users. Our method signif- icantly improves the performance of applications with heavily im- balanced workloads, and enables trade-offs between workload im- balance and ALU underutilization for fine-tuning the performance.
Our evaluation reveals that our method exhibits up to 9x speedup over previous GPU algorithms and 12x over single thread CPU execution on irregular graphs. When properly configured, it also yields up to 30% improvement over previous GPU algorithms on regular graphs. In addition to performance gains on graph algo- rithms, our programming method achieves 1.3x to 15.1x speedup on a set of GPU benchmark applications. Our study also confirms that the performance gap between GPUs and other multi-threaded CPU graph implementations is primarily due to the large difference in memory bandwidth.


http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F6067545%2F6075092%2F06075214.pdf%3Farnumber%3D6075214&authDecision=-203
A modified parallel approach to Single Source Shortest Path Problem for massively dense graphs using CUDA, 2011
Today's Graphics Processing Units (GPUs) possess enormous computation power with highly parallel and multithreaded architecture, and the most attractive feature being their low costs. NVIDIA's CUDA provides an interface to the developers to use the GPUs for General Purpose Parallel Computing. In this paper, we present a modified algorithm of Single Source Shortest Path Problem on GPU using CUDA. First, we modify the standard BELLMAN-FORD algorithm to remove its drawbacks and make it suitable for parallel implementation, and then implement it using CUDA. For dense graphs, our Algorithm gains a speedup of 10×–12× over the previously proposed parallel algorithm. Our Algorithm also accept graphs with negative weighted edges and can detect any reachable Negative Weighted Cycle, which widens its scope to accept generalized problems.


http://www.springerlink.com/content/a254839r565r176p/
CUDA Solutions for the SSSP Problem
We present several algorithms that solve the single-source shortest-path problem using CUDA. We have run them on a database, composed of hundreds of large graphs represented by adjacency lists and adjacency matrices, achieving high speedups regarding a CPU implementation based on Fibonacci heaps. Concerning correctness, we outline why our solutions work, and show that a previous approach [10] is incorrect.


http://ldc.usb.ve/~vtheok/cursos/ci6323/pdf/lecturas/Accelerating%20Large%20Graph%20Algorithms%20on%20the%20GPU%20Using%20CUDA.pdf
Accelerating Large Graph Algorithms on the GPU Using CUDA, Pawan Harish and P.J. Narayanan,

Largegraphsinvolvingmillionsofverticesarecommoninmanyprac- tical applications and are challenging to process. Practical-time implementations using high-end computers are reported but are accessible only to a few. Graphics Processing Units (GPUs) of today have high computation power and low price. They have a restrictive programming model and are tricky to use. The G80 line of Nvidia GPUs can be treated as a SIMD processor array using the CUDA pro- gramming model. We present a few fundamental algorithms – including breadth first search, single source shortest path, and all-pairs shortest path – using CUDA on large graphs. We can compute the single source shortest path on a 10 million vertex graph in 1.5 seconds using the Nvidia 8800GTX GPU costing $600. In some cases optimal sequential algorithm is not the fastest on the GPU architec- ture. GPUs have great potential as high-performance co-processors.


----

http://sc.chat-shuffle.net/paper/uid:110006828689
CUDAによる全点対最短経路問題の高速化(アプリケーション高速化,「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2008))
本論文では全点対最短経路(APSP:All-Pairs Shortest Path)問題をGPU(Graphics Processing Unit)を用いて高速化した結果を述べる.提案手法は,GPUで動作するプログラムをGPU向けの開発環境CUDA(Compute Unified Device Architecture)を用いて記述する.アルゴリズムには単一始点最短経路を繰り返し求める手法(SSSP反復法)を用いる.問題全体での逐次処理を減らしてより高い速度向上を得るために,1っのSSSP問題を1つのタスクとし,それらのタスクを並列処理する.さらに,共有メモリを用いてタスク間でデータを共有し,グローバルメモリの参照を削減する.結果,既存手法よりも3.5〜18倍高速であった.また,SSSP反復法の性能がグラフの特性に依存して変動することを示す.
http://hagi-www.ics.es.osaka-u.ac.jp/research/papers/200812_t-okuyam_ispa.pdf

2011年11月19日土曜日

[Graph500] Graph500 on Amazon EC2

Graph500 on Amazon EC2 に関して

- Amazon EC2 のクラスタインスタンスの仕様
Amazon EC2 supports Cluster instance"
Xeon X5570 (2.95GHz), 23 GB of RAM, 1690 GB of local
storage, and 10 Gbps network, all for $1.60 per hour  recently GPU (Tesla Fermi) is available
(2010年後半の仕様なので変化があるはず)

- 研究内容
- 仮想化環境において Graph500 を実行し、bare metal の環境との性能特性を行う
- ベンチマークを完遂させることを目的としない。BFS を何回か、validation は実行しない。
- Scale は 1ノードにつき Scale 26でいけるので、TSUBAME で取った性能プロファイルと比較できる
- マイクロベンチマークを実行し、ネットワークトポロジー予測を行う(関連研究があるはずなので調査)
- CPU 課金が1時間単位なのでノード数を少なくできるか?
- 予測トポロジーに応じて、MPI のランク最適配置を計算し、性能を向上させる
- 128ノードを用いて12時間走らせて約20万円
- 上記研究内容をもとに、Amazon が Graph500 にサブミッションするかどうかは別の話し
- Target Conference: IEEE Cloud 2012 締め切りは 2012年1月後半

[参考文献]
http://www.stratosphere.eu/files/TopologyInferenceEnd2End_11.pdf

http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5948654

http://dl.acm.org/citation.cfm?id=1833691
The impact of virtualization on network performance of amazon EC2 data center, InfoCOM 2010

Cloud computing services allow users to lease computing resources from large scale data centers operated by service providers. Using cloud services, users can deploy a wide variety of applications dynamically and on-demand. Most cloud service providers use machine virtualization to provide flexible and costeffective resource sharing. However, few studies have investigated the impact of machine virtualization in the cloud on networking performance.

In this paper, we present a measurement study to characterize the impact of virtualization on the networking performance of the Amazon Elastic Cloud Computing (EC2) data center. We measure the processor sharing, packet delay, TCP/UDP throughput and packet loss among Amazon EC2 virtual machines. Our results show that even though the data center network is lightly utilized, virtualization can still cause significant throughput instability and abnormal delay variations. We discuss the implications of our findings on several classes of applications.

[Graph500] 住元さんとの議事録

SC2011 にて住元さんとミーティング。以下、上野君が取ってくれた議事録

通信性能は、1本あたり4.7GB/5GB。1ノード全部で14.7GB。
ジョブごとにセグメントを分けている
6次元なのでホップ数はx,y,zにそれぞれ+2したもの
K用のプロファイリングツールがある
6次元での位置や故障ノードのなどの情報はユーザに見せていない
3次元では遠いノードでも、6次元なのでショートカットが存在する
3次元で遠いノードほど、ショートカットがある
実行中にノードが故障したら割り当て範囲内で再配置して実行
キャッシュセグメント?(明示的にキャッシュを制御する?)
プログラムからはローカルディスクしか見えない
ローカルディスクは32ノードに対して1RAIDシステム
15000回転のHDD 16台のRAID 4+1
接続はFiberChannel
メモリのデータをすべてダンプするだけの容量くらいはもちろんある
キャッシュインジェクションにより低レイテンシ(Infinibandにはない)
RDMAなので、最終的にはメモリに書き込まれる
普通はDMAでメモリに書き込まれたらキャッシュはフラッシュされる
キャッシュラインに全部書き込めばメモリから読み込まれることはない
通信モジュールは入出力合わせて100GB/s
富士通のユーザフォーラム SSけん HPC forum おいなが

2011年6月21日火曜日

[Graph500] 最適化に向けて

Network Coding や、Stream Algorithms の Lossy Count による最適化。
如何にメモリに載り切らない大規模グラフを扱うか。 スケールフリー性を利用し、記憶装置の各階層に記憶,などなど。

2011年6月20日月曜日

[Graph500] 90%

IISWC への論文投稿に向けて、土日のほとんどの時間、書き続け、完成度は90%ぐらいになった。今週の平日は来週からの出張に向けていろいろごたごたしているので、ペースは下がるが、提出できそうだ。

2011年6月19日日曜日

Running Large Graph Algorithms - Evaluation Of Current State-Of-The-Art And Lessons Learned

"Running Large Graph Algorithms - Evaluation Of Current State-Of-The-Art And Lessons Learned"
http://highscalability.com/blog/2010/3/30/running-large-graph-algorithms-evaluation-of-current-state-o.html

LLNL の Andy Yoo のトーク

[Graph500] 論文仕上げ

 今日の目標はデータを差し替える以外はすべて完成させること。

15:00 残りはabstract, イントロ、関連研究の半分、Graph500概要(グラフ生成の部分)

[TSUBAME] Installing MVAPICH2

TSUBAME 上にインストールされている MVAPICH2のバージョンは 1.5.1 と古いので、1.6をホームにインストール
% ./configure --prefix=$HOME/packages/mvapich-1.6 --with-rdma=gen2; make; make install

α版だが、1.7a2 もインストール
% ./configure --enable-smpcoll --with-rdma=gen2

2011年6月18日土曜日

Oprofile

下記、Oprofile の使い方の例。Sleep 時間(プロファイリング取得時間)、CPU イベントタイプ、カーネルのデバッグシンボル(VMLINUX) の場所は適当に変えてください。CPUイベントの種類は "opcontrol --list-events " で確認できます。



#!/bin/bash

if [ $# -eq 1 ];
then
DIR=$1
else
DIR=results
fi

if [ ! -e $DIR ];
then
mkdir $DIR
fi

# sc02 の場合
VMLINUX=/usr/lib/debug/lib/modules/2.6.18-92.el5/vmlinux

#opcontrol --setup --no-vmlinux
opcontrol --setup
opcontrol --shutdown
opcontrol --setup --vmlinux=$VMLINUX
opcontrol --reset
opcontrol --separate=none


opcontrol --event=default
## opcontrol --event=PM_INST_CMPL_GRP1:100000:0:1:1 --event=PM_RUN_CYC_GRP1:100000:0:1:1 --event=PM_INST_DISP_GRP1:100000:0:1:1
opcontrol --start
sleep 30
opcontrol --shutdown
opreport > $DIR/cycle.out
opreport -l > $DIR/cycle_l.out
#opreport --callgraph > $DIR/callgraph.out
#opreport --symbols > $DIR/symbols.out
opcontrol --reset

2011年6月16日木曜日

[Graph500] IISWC 2011

目標としては明日の早朝までに 1/3 ぐらいまでに仕上げる予定。但し、作業開始時間は午後7時頃から.

2011年6月13日月曜日

[Graph500] Code reading

 渡部君、上野君が頑張っていますが、Graph500のリファレンス実装の中身が段々と分かってきました。直近のワークとしては、性能特性を調べることですが、「クロネッカーグラフの特性を活用した頂点配置を実行し、通信最適化による性能向上を達成する」が一つの研究テーマになるでしょう。

2011年6月4日土曜日

[ExaGraph] SGRACE: Streaming Graph Clustering Algorithm

LLNL (Lawrence Livermore National Laboratory) の研究者 Andy Yoo による大規模グラフ解析に関する研究

Evaluating Use of Data Flow Systems for Large Graph Analysis, Andy Yoo
http://dsl.cs.uchicago.edu/MTAGS09/a05-yoo-slides.pdf

A New Benchmark For Evaluation Of Graph-Theoretic Algorithms, CORR2010
Parallel Generation of Massive Scale-Free Graphs, CORR2010
Scalable Analysis of Massive Graphs on a Parallel Data Flow System, HICSS2010


Google での講演: http://www.youtube.com/watch?v=PBLgUBGWcz8

[ExaGraph] Graphs and HPC: Lessons for Future Architecture

Graphs and HPC: Lessons for Future Architectures, Bruce Hendrickson (Sandia)

http://science.energy.gov/~/media/ascr/ascac/pdf/meetings/oct08/hendrickson_ascac.pdf

Cray のアーキテクチャに偏ったスライド. BlueGene/L との比較も少しあり。

グラフ解析問題の特徴
Runtime is dominated by latency
Potentially random accesses to global address space
Perhaps many at once, but parallelism is fine-grained
Essentially no computation to hide memory costs
Access pattern is data dependent
Prefetching unlikely to help
Usually only want small part of cache line –
levels of memory all Potentially abysmal locality at hierarchy

以上のグラフ解析の要件を満たすアーキテクチャ
Low latency / high bandwidth for small messages!
Latency tolerant
Light-weight synchronization mechanisms
Global address space
- Obviate the need for partitioning –
- Avoid memory-consuming profusion of ghost-nodes –
- No local/global numbering conversions –
- Support fine-grained parallelism –
- One machine with these properties is the Cray MTA-2, XMT